Reason for JFET is always reverse biased
Due to “depletion region” surface reduction increases the resistance of the drain source and reduces the current flow and so JFET is always reverse biased.
This bias leads to the formation of a “depletion layer” within the channel and the width of which increases with bias.
The amplitude of the current flowing through the channel between the drain terminals and the source is controlled by a voltage applied to the Gate terminal, which is inverted.
Three types of bias are self-bias, voltage-divider bias, and current-source bias.
The JFET operates with a reverse-biased pn junction with high input resistance due to the reverse-biased gate-source junction.
“depletion region” to form around the PN junction of the JFET. Since this region has a small number of current carriers, the inverse polarity effect is to reduce the effective cross sectional area of the “channel”.
Applying a sufficiently large negative voltage to the gate will cause the drain region to become so large that the conduction of the current through the bar will stop completely.
The voltage required to reduce the drain current (ID) to zero is called “pinch-off” voltage and is comparable to the “cut-off” voltage in a vacuum tube.
In the figure, the 1 volt negative applied, although not large enough to completely arrest the conduction, caused a marked decrease in the drain current (from 10 milli amperes to zero gate polarization conditions at 5 milli amperes).
The calculation shows that the 1-volt gate bias also increased the JFET resistance (from 500 ohm to 1 kilohm).
In other words, a 1 volt variation in gate voltage doubled the resistance of the device and reduced the current flow to half.
These measures, however, only show that a JFET operates in a way similar to a bipolar transistor, even though the two are constructed differently.
As stated above, the main advantage of a FET is that its input impedance is significantly higher than that of a bipolar transistor.